1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise complex gate electrode structures based on a high-k gate dielectric.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations produced by volume production techniques. One reason for the dominant role of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, during anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon and/or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to, among other things, an increased leakage current. Aggressively scaled transistor devices with a relatively low supply voltage, and thus reduced threshold voltage, may suffer from an exponential increase of the leakage current, since the required increased capacitive coupling of the gate electrode to the channel region is achieved by reducing the thickness of the silicon dioxide layer. For example, a channel length of approximately 80 nm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, the usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical circuit portions, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance driven circuits, even if only transistors in speed critical paths are formed on the basis of an extremely thin gate oxide.
Therefore, various measures have been proposed for increasing the dielectric strength and the effective dielectric constant of the silicon dioxide material, such as performing treatments on the basis of nitrogen in order in incorporate a certain amount of nitrogen. Although these treatments of the base oxide material provide significant improvements, the further scaling of the transistor dimensions may demand even further sophisticated approaches. To this end, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide-based gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide-based layer. Hence, for obtaining a desired reduced capacitance equivalence thickness (CET) of the gate dielectric material of, for instance 1.2 nm or less, referring to a silicon oxide material, it has been thus suggested to replace at least a portion of the conventional silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), having a k of about 21, HfSiO, zirconium oxide (ZrO2), TiO2 and the like.
Additionally, transistor performance may be increased by providing an appropriate conductive material for the gate electrode so as to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides an increased capacitance based on the same or greater thickness as a silicon dioxide-based layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, the non-polysilicon material, such as titanium nitride and the like, may be formed so as to connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone.
Consequently, a plurality of process strategies have been developed in order to form high-k metal gate electrode structures with appropriate work function for different types of transistors, wherein a reduced capacitance equivalent thickness (CET) is obtained that corresponds to extremely sophisticated silicon dioxide-based gate dielectric materials, while, on the other hand, the actual physical thickness may be increased in order to reduce the gate leakage currents that would otherwise be associated with the extremely silicon dioxide-based gate dielectrics. Since, typically, the high-k dielectric materials are very sensitive with respect to exposure to certain process atmospheres, in many approaches, the high-k dielectric material in combination with appropriate metal-containing electrode materials and work function metals are provided in a very late manufacturing stage in which gate electrode structures having the desired lateral dimensions are used as dummy gate electrode structures during the entire manufacturing flow for completing the basic transistor configuration. Thereafter, portions of the gate electrode structures are removed so as to expose the channel region of the different transistors in order to form thereon an appropriate gate dielectric material including a material of increased dielectric constant, followed by appropriate metal species for obtaining a desired work function and superior conductivity of the resulting gate electrode structures. Although this approach may result in a reduced CET of the gate electrode structures at acceptable gate leakage currents, very complex and complicated patterning, deposition and planarization techniques are required in order to remove unwanted gate materials and provide the various gate layers in a well-defined thickness and material composition in the gate electrode structures. For these reasons, in other very promising approaches, the high-k dielectric material in combination with appropriate metal species for defining the work function of the gate electrode structures for different types of transistors may be provided in an early manufacturing stage, wherein specific treatments of the high-k dielectric material and/or the metal layer formed thereon may be implemented in order to adjust and subsequently stabilize the characteristics of the gate electrode structures. To this end, in some approaches, the high-k dielectric material is formed on a thin silicon dioxide-based dielectric material in order to form a combined gate dielectric layer having a desired reduced CET with a physical thickness that is sufficient to retain acceptable gate leakage currents. Thereafter, adjustment of the work function for different types of transistors may be accomplished by providing different types of diffusion layers above the active regions of the different transistors in order to initiate a diffusion process on the basis of a subsequent heat treatment at temperatures of approximately 800° C. and higher, thereby efficiently driving a respective metal species into the underlying gate dielectric layer. For example, US patent application publication 2010/0327373, with the title “Uniform High-k Metal Gate Stacks by Adjusting Threshold Voltage for Sophisticated Transistors by Diffusing a Metal Species Prior to Gate Patterning,” the entire disclosure of which is incorporated herein by reference, describes a process sequence in which different metal species, such as lanthanum and aluminum, may be incorporated into the gate dielectric layers of N-channel transistors and P-channel transistors by applying an efficient deposition, patterning and masking regime in order to perform a diffusion process at elevated temperatures. Thereafter, any cap layers and diffusion layers are removed and a common metal-containing electrode material, such as titanium nitride, is formed above the selectively adjusted gate dielectric layers, followed by a further electrode material, such as silicon. During the further processing, the sensitive high-k dielectric material may be efficiently encapsulated, for instance, by providing appropriate liners or sidewalls spacers, thereby substantially avoiding unwanted interaction with reactive process atmospheres, such as wet chemical cleaning processes, anneal atmospheres including a certain amount of oxygen and the like.
Generally, this so-called “gate first” approach may result in a highly efficient overall process flow since many well-established concepts, for instance with respect to gate patterning on the basis of sophisticated lithography and etch techniques, may still be used irrespective of the presence of the moderately thin high-k gate dielectric layer, while, on the other hand, extremely complex process steps with respect to replacing gate materials and forming the high-k dielectric material at a very late manufacturing stage may be avoided.
In an attempt to further reduce the CET of the gate electrode structures, any straightforward strategies, such as simply reducing the thickness of the high-k dielectric material, may concurrently increase the gate leakage currents since this may result in a reduction of the physical thickness and, thus, of the charge carrier blocking capabilities of the resulting gate dielectric materials. On the other hand, transistor performance is inversely proportional to the CET and hence corresponding reduction of CET is mandatory in further improving overall transistor performance. In this respect, it has been recognized that by exposing the high-k dielectric material to elevated temperatures, for instance of approximately 800° C. and significantly higher, the CET may be reduced, however, without unduly affecting the gate leakage current behavior of the gate dielectric material. To this end, it has been proposed to perform a heat treatment or anneal process immediately after the deposition of the high-k dielectric material in order to provide superior stability and reduced CET. Upon applying an appropriate process strategy as required in volume production techniques, however, it has turned out that the resulting improvement in CET is significantly less than expected.
In view of the situation described above, the present disclosure relates to process techniques for providing sophisticated high-k metal gate electrode structures, while avoiding or at least reducing the effects of one or more of the problems identified above.